Physical Design Engineer Job Listing at AMD in Santa Clara, CA (Job ID 63112-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing changes, functional ecos, LEQ, helping construct/modify flows, timing analysis and timing closure.

THE PERSON:

Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams

KEY RESPONSIBILTIES :

This engineer will work on high speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED EXPERIENCE:

• Strong experience in high speed multi-gigabit SerDes PHY designs or other high performance IP designs
• Hands-on experience in all aspects of timing closure in high-performance designs using sub-micron technologies.
• Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise, cross-talk, and cross-corner variation.
• Comfortable constraining timing paths using SDC and TCL.
• Familiar with creating functional and timing ECOs and verifying logical equivalence using Formality.
• Exposure to RTL, synthesis, logic equivalence, DFT, floor-planning, and backend-related methodology and tools such as ICC2 and Fusion Compiler.
• Basic understanding of scripting languages (Python and Perl) and design automation using TCL.
• Knowledge of SSB timing is a plus.
• Strong communication skills and can accurately describe issues cross-functionally to different teams (RTL design, verification, DFT, AMS) at an appropriate level of detail

ACADEMIC CREDENTIALS:

• Major in EE, CS or related, Master Degree preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs

LOCATION: Santa Clara, CA

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.