Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a Server Silicon Data Analyst, you will enable entitlement outcomes for AMD server products by transforming Sort, Final Test, and SLT data into actions. You'll define and execute data‑driven characterization strategies across PVT corners, partner with Product/DFT/Test to ensure coverage meets yield, test time, quality, and schedule targets, and drive post‑silicon debug closure using analytics, automation, and clear storytelling.
THE PERSON:
- Self‑starter passionate about advanced semiconductor data and products
- Thrives in dynamic, high‑performance, fast‑changing environments; forward‑thinking mindset
- Anticipates risks and opportunities; proactively shapes data‑driven product strategies
- Strong problem‑solving and structured debug skills using data
- Effective communicator; collaborates across globally distributed teams
- Able to influence across Fab, Test, DFT, Design, Quality, Platform
- Team‑oriented, supportive, and collaborative
- Continuous‑improvement mindset; delivers “next 5%” enhancements
KEY RESPONSIBILITIES:
- Coverage & Requirements
Translate product requirements into measurable test coverage and pre‑silicon pattern requirements; collaborate with DV/DFT to align ATPG/MBIST/JTAG/at‑speed data outputs with product goals. - Characterization Analytics
Build and execute characterization analysis plans (Sort & Final Test across PVT) to determine optimal test points, guardbands, and binning strategies. - Yield, Quality & Test Time
Use statistical methods to monitor entitlement gaps, quantify impact, and implement actions to improve yield, reduce DPPM, and optimize test time across Sort/FT/SLT. - Post‑Silicon Debug
Apply structured data analysis to accelerate process, device, and yield issue debug and closure in partnership with Fab, Product, Platform, and Test Engineering. - Automation & Visibility
Develop JMP/Python workflows, dashboards, and reports for recurring analyses (SPC, outliers, trend break detection, screening efficiency). - “Next 5%” Improvements
Identify and deliver incremental (‘next 5%') enhancements to requirements clarity, entitlement tracking, data reliability, and workflow efficiency.
Illustrative outcomes: +2–5 pp yield uplift on early lots, −10–20% test time on stabilized flows, ≥25% reduction in repeat‑test‑induced escapes, measurable DPPM reduction aligned to customer targets.
MINIMUM QUALIFICATIONS:
- Experience in product/test/semiconductor data analysis or product engineering analytics
- Proficiency with statistical analysis and data tooling (e.g., JMP, Python/pandas); capable of building reusable analytics/automation
- Experience with characterization and test point optimization (guardbanding, PVT coverage, screening effectiveness)
- Understanding of semiconductor process, packaging, and test technologies
- Demonstrated ability to drive cross‑functional closure with Fab/Design/DFT/Test/Quality
- Clear communicator who can convert complex data into decisions and actions
PREFERRED EXPERIENCE:
- Familiarity with DFT data: ATPG scan, MBIST, JTAG, at‑speed test; integration with ATE flows
- ML exposure applied to production/test data (e.g., anomaly detection, outlier screening, test time prediction, adaptive test) using Python/scikit‑learn/AutoML
- Experience with SPC, control charts, and production monitoring at scale
- Server‑class devices and performance binning strategies
- Semiconductor fabrication process optimization or device performance validation exposure
ACADEMIC CREDENTIALS:
- B.S./M.S. in Electrical or Computer Engineering, or related field (e.g., CE/ECE/Data‑focused disciplines) or equivalent experience
This role is not eligible for visa sponsorship.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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