RTL DESIGN ENGINEER Job Listing at AMD in San Jose, CA (Job ID 71668-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

We are seeking a Logic Design Expert with strengths in RTL and Timing and preferably with a background in DFx.

You have had significant success driving Design Methodologies, RTL, Timing and Architecture to tape out and production. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This role will stretch you as you lead design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design, verification, validation, CAD and product engineering teams.

THE PERSON:  

You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:  

• Take full ownership of a critical IP that is used by every block in AMD's FPGA SOCs as an anchor for all DFx functions. Responsibilities include:
  • Owning Architecture, Specifications and RTL of the IP
  • Co-owning Timing and Design Quality Checks (and waivers) for the IP
• Work cross functionally with DFx execution and verification teams to enable integration and validation of IP in all phases of design implementation flow
• Work closely with Design teams for Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
• Engage with validation and product teams on test plan, coverage, Silicon bring up and silicon debug
• Contribute to front-end, DFx and timing methodologies
• Drive innovation in a rapidly changing technological environment

PREFERRED EXPERIENCE:  

• Strong foundation in logic design, switching theory and timing
• Demonstrated expertise with design tools and design flows
• Experience with supporting silicon debug and diagnosis
• Skilled at collaborating with teams across different geographies
• Experienced in SoC and IP level DFx architecture, IP and methodologies
• Expertise in one or more of the following: Clocks, Resets, Harvesting, Yield, Scan, ATPG, MBIST, Repair, Yield, Power Management
• Understanding of 1149.1 / 1687 standards

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in Computer Engineering/Electrical Engineering 

LOCATION: San Jose, CA 

#LI-DW1

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.