Senior Front End Integration -STA Engineer Job Listing at AMD in Hyderabad, Telangana (Job ID 65220-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SENIOR SILICON DESIGN ENGINEER 

THE ROLE: 

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES: 

Front-end implementation from RTL to netlist, including RTL Lint, CDC/RDC analysis, timing constraints, Power Analysis, STA for Multi-Media IP's

• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
• Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
• Analyze the inter-block timing and come up with IO budgets for the various partition blocks.
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC.
• Perform RTL Lint and work with the Designers.
• Analyze RTL CDC/RDC and work with Designer for potential Clock and Reset Design Domain crossing issues. 
• Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults.
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
• Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
• Implementing Functional ECO's using Conformal and writing manual Eco's.
• Work with Architects, RTL Designers and SOC teams for efficient IP Quality.

PREFERRED EXPERIENCE: 

• 5 to 10 years of experience in Front-end implementation from RTL to netlist 
• Familiarity with Power Analysis 
• Experience/Background on Computing/Graphics is a benefit 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.