Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Push Boundaries, Deliver Innovation and Change the World! In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team also is responsible for the Design and Verification of several critical as well as the integration to other subsystems and SOC. The Design and Design Verification groups within this team are also responsible for developing a balanced architecture between power consumption and performance, delivering high complexity RTL code and creating advanced testbenches using cutting edge verification techniques.
THE PERSON:
- Strong analytical and problem solving skills with a pronounced attention to detail
- Strong communication, mentoring and leadership skills
- Skilled at driving team and tasks from start to completion with superior quality
- Can work well with cross functional teams
KEY RESPONSIBLITIES:
Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
PREFERRED EXPERIENCE:
Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
Experience with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal, VSI/VC-static, Formality, etc…)
Experience with unix/linux and scripts (tcl, perl, etc.)
Experience with physical design is a plus.
Has Synthesis or physical implement experience.
Experience with lower power design methodology.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer Engineering/Electrical and Electronics Engineering
LOCATION:
Penang, Malaysia
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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